There was a time in which everybody believed that PLL (phase-locked loop) is the best of Oscillators. A PLL is a current or voltage-driven oscillator which is constantly adjusted in order to match the phase of the frequency of an input signal. Basically a PLL is an self-controlled servo-loop. But today it is frequency synthesisers that hold the title of the 'best oscillator'. A single reference frequency is enough for a frequency synthesiser to generate a range of frequencies. The functioning of PLL circuit is like that of a driver who keeps his car steady at a particular speed which he is duly directed to maintain every time. A PLL basically contains a VCO (Voltage Controlled Oscillator), an Error Detector and a Low pass Filter in it. It is at the input portion of the PLL where VCO is set that all harmonics and distortion elements are free to report. If it is to 455 KHz that the PLL is set, the reference voltage at the Error Detector will change itself accordingly so that only 455 KHz. passes through and every other signal is suppressed. Here, Error Detector uses its' own discretionary ability to stay tuned to the set frequency.
It is in connection with Coherent CW (strictly timed morse code) that PLL was first experimented. CCW can be said to be the output of intense experiments done to make maximum communication tracks in every fraction of the allotted band spectrum. CCW could reduce the bandwidth of an incoming signal by half. It gave birth to more coherent styles. The possibilities of PLL is not limited to just Oscillators and Filters. They are used in modulation/demodulation power/voltage limiter circuits also. PLLs also have become unavoidable in Microwave, Satellite and VHF communication equipments.
As mentioned early, the voltage at the Error Detector of a PLL changes so that it can prevent any frequency change in the input port of the PLL VCO. The Phase loop remain locked to only that intended frequency. This property of the PLL circuit is called 'tracking'. In PLL it is the lowpass filter that works as noise suppressors. The tracking accuracy of a PLL is usually 100 to 100 fold when compared to general gadgets of the same function. Depending upon the type of perfect Integrator in PLL VCOs PLL s are classified into First Order Loop and Second Order loop. Even the low pass filters in PLLs are found in active and passive categories. Those Active Filter PLLs used in Op-amps (Operational Amplifier) ICs are best for tracking. A PLL's frequency stabilisation capabilities are not unlimited as anyone may assume it to be. PLLs are unable to function at a frequency change beyond a particular limit. The frequency range to which a PLL is set is called its' 'locking range'. The functioning of the locking system in it is called 'capture process'. There are various acquisition methods used for capture process.
Frequency Modulation is done directly feeding the modulation intelligence into the control port of the VCO in a PLL. During demodulation, the change in the Error Detector reference voltage which is in proportion to the input frequency changes is used as detected intelligence. If PLL system is used in the IF stage of FM Receivers, no other circuitry is needed for limiting and bandwidth control activities. In AM receivers, Coherent PLL Detectors which are many folds better than the common diode detectors can be used. PLL s have the exclusive ability to identify and sort out the desired frequencies that are hid among powerful distortion signals. In Karaoke 'sing alone' mode, the singer or a particular instrument is erased giving chance to a new singer or instrumentalist to interrupt in. Here also PLL is the hero. It is because input and output power in a PLL is not related in proportion that output power stability also is possible in a PLL.
Frequency Synthesising using PLL belongs to Indirect Class. In Direct Class output frequency will only be in steps of the reference voltage at the Error Detector in a PLL. It is either harmonics of the input frequency or those in steps of the reference voltage in the Error Detector that are formed in 'Divide by N loop pattern.' Signals that are not related to the reference frequency in multiple or division are formed in 'Fractional N loop' method. I hope that no reader will find that these brief illustrations on PLLs wont ever be inappropriate to any enthusiastic reader.
Today a lot of ICs competent to replace the conventional IF circuits in a Receiver have begun flooding the components market. Now, a single ICs is enough to function simultaneously as IF amplifiers, Bandwidth limiters, Noise blankers, Product detectors, Preamplifiers etc. A Receiver IF stage circuit using IC TA 7640 IC is shown in C-10/1.
If it is CW or SSB signal that comes through the IF stage, instead of the regular envelop detector, we need a product detector that demodulates audio from a signal mixed with the BFO signal. There are three types of Mixer circuits - single ended, single balanced and double balanced mixers (DBM). Even though single ended mixers are enough for a radio in the regular environment, double balanced mixers offer much more excellent performance. In DBM circuits the input - output isolation is higher and the fundamental frequencies and its harmonics are suppressed. All that are produced in the output are the difference and the sum of both the frequencies mixed. Instead of a diplexer circuit that absorbs all the unwanted signals at the mixer output, in DBMs a simple tuned circuit is enough. In C-10/2, a DBM circuit using MC 1496 (G) is shown.
It is the AGC (Automatic Gain Control) in the IF stage IF that maintains the dynamic range of a Receiver by bringing both a powerful signal and a weak signal at more or less a standard strength level.
The first step of creating an effective AGC is rectifying the AC signal at the output of the IF stage and converting it into dc pulses just like an eliminator rectifies the ac cycles. Further, this dc pulse is fed back into the base of the first IF Amplifier.
Here, if the AGC voltage fed back is high, the transistor gain will be reduced. There it acts like a degenerative feedback. In advanced receivers there are facilities to break the AGC at very weak signals and regulate the AGC voltage for very strong RF signals.
In C-10/4 the circuit diagram of an IF stage with AGC control facility is given. A typical method of regulating bandwidth without increasing the active IF sages also are incorporated in this circuit. Another peculiarity if this circuit is that it has an ANL (Automatic Noise Limiter) circuit also attached to the IF. This can clamp all Pulse type noises at voltages below 0.7. This clamping circuit can be attached to the front RF stage itself.
Frequency Synthesising using PLL belongs to Indirect Class. In Direct Class output frequency will only be in steps of the reference voltage at the Error Detector in a PLL. It is either harmonics of the input frequency or those in steps of the reference voltage in the Error Detector that are formed in 'Divide by N loop pattern.' Signals that are not related to the reference frequency in multiple or division are formed in 'Fractional N loop' method. I hope that no reader will find that these brief illustrations on PLLs wont ever be inappropriate to any enthusiastic reader.
Today a lot of ICs competent to replace the conventional IF circuits in a Receiver have begun flooding the components market. Now, a single ICs is enough to function simultaneously as IF amplifiers, Bandwidth limiters, Noise blankers, Product detectors, Preamplifiers etc. A Receiver IF stage circuit using IC TA 7640 IC is shown in C-10/1.
If it is CW or SSB signal that comes through the IF stage, instead of the regular envelop detector, we need a product detector that demodulates audio from a signal mixed with the BFO signal. There are three types of Mixer circuits - single ended, single balanced and double balanced mixers (DBM). Even though single ended mixers are enough for a radio in the regular environment, double balanced mixers offer much more excellent performance. In DBM circuits the input - output isolation is higher and the fundamental frequencies and its harmonics are suppressed. All that are produced in the output are the difference and the sum of both the frequencies mixed. Instead of a diplexer circuit that absorbs all the unwanted signals at the mixer output, in DBMs a simple tuned circuit is enough. In C-10/2, a DBM circuit using MC 1496 (G) is shown.
It is the AGC (Automatic Gain Control) in the IF stage IF that maintains the dynamic range of a Receiver by bringing both a powerful signal and a weak signal at more or less a standard strength level.
The first step of creating an effective AGC is rectifying the AC signal at the output of the IF stage and converting it into dc pulses just like an eliminator rectifies the ac cycles. Further, this dc pulse is fed back into the base of the first IF Amplifier.
Here, if the AGC voltage fed back is high, the transistor gain will be reduced. There it acts like a degenerative feedback. In advanced receivers there are facilities to break the AGC at very weak signals and regulate the AGC voltage for very strong RF signals. In C-10/4 the circuit diagram of an IF stage with AGC control facility is given. A typical method of regulating bandwidth without increasing the active IF sages also are incorporated in this circuit. Another peculiarity if this circuit is that it has an ANL (Automatic Noise Limiter) circuit also attached to the IF. This can clamp all Pulse type noises at voltages below 0.7. This clamping circuit can be attached to the front RF stage itself.
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